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cy7c43646 cy7c43666 cy7c43686 1k/4k/16k x36/x18x2 tri bus fifo cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 july 28, 2000 features ? high-speed, low-power, first-in first-out (fifo) memo- ries w/ three independent ports (one bidirectional x36, and two unidirectional x18) 1k x36/x18x2 (cy7c43646) 4k x36/x18x2 (cy7c43666) 16k x36/x18x2 (cy7c43686) 0.35-micron cmos for optimum speed/power high speed 133-mhz operation (7.5-ns read/write cycle times) low power ?i cc = 100 ma ?i sb = 10 ma fully asynchronous and simultaneous read and write operation permitted mailbox bypass register for each fifo parallel and serial programmable almost full and almost empty flags retransmit function standard or fwft mode user selectable partial reset big or little endian format for word or byte bus sizes 128-pin tqfp packaging easily expandable in width and depth logic block diagram port a control logic port b control logic mail1 register input register write pointer read pointer status flag logic programmable timing mode status flag logic read pointer write pointer 1k/4k/16k dual ported memory 256/512/1k 4k/16k x36 dual ported memory mail2 register output register input register fifo1, mail1 reset logic fifo2, mail2 reset logic clka csa w/ra ena mba rt2 mrs1 prs1 ffa /ira afa spm fs0/sd fs1/sen a 0 ? 35 efa /ora aea mbf2 mrs2 prs2 ffc /irc afc be/fwft b 0 ? 17 clkb csb renb mbb sizeb rti efb /orb aeb mbf1 output register bus matching common port logic (b and c) be output c 0 ? 17 port c control logic clkc wenc mbc sizec bus matching input flag offset registers x36
cy7c43646 cy7c43666 cy7c43686 2 pin configuration cy7c43646 cy7c43666 cy7c43686 tqfp top view 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 fs0/sd mrs2 fs1/sen gnd clkc mrs1 mba mbf2 aea afa v cc prs1 efa /ora ffa /ira csa renb wenc csb gnd ffc /irc efb /orb afc aeb v cc mbf1 mbb 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 c 12 c 8 c 9 c 10 c 11 c 13 mbc gnd c 14 c 15 c 16 c 17 v cc prs2 clkb gnd sizec b 16 b 17 c 0 c 1 c 2 c 3 c 4 c 5 gnd sizeb c 6 c 7 rt1 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 a 2 b 0 gnd a 0 a 1 v cc spm a 3 a 4 a 5 gnd a 6 a 7 a 8 a 9 b 9 b 8 b 7 v cc b 6 gnd b 5 b 4 b 3 b 2 b 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 v cc a 29 gnd a 30 a 31 a 32 a 34 a 35 gnd clka ena w/ra a 12 a 20 gnd a 18 a 19 a 21 v cc a 22 gnd be/fwft a 23 a 24 a 25 a 26 a 27 a 28 a 33 72 71 70 69 68 67 66 65 b 12 b 10 b 11 gnd b 13 b 14 b 15 v cc 30 31 32 33 34 35 36 37 38 rt2 a 10 a 11 gnd a 13 a 14 a 15 a 16 a 17
cy7c43646 cy7c43666 cy7c43686 3 functional description the cy7c436x6 is a monolithic, high-speed, low-power, cmos bidirectional synchronous (clocked) fifo memory which supports clock frequencies up to 133 mhz and has read access times as fast as 6 ns. two independent 1k/4k/16k x 36 dual-port sram fifos on board each chip buffer data in opposite directions. fifo data on port b can be input and output in 36-bit, 18-bit, or 9-bit formats with a choice of big or little endian configurations. the cy7c436x6 is a synchronous (clocked) fifo, meaning each port employs a synchronous interface. all data transfers through a port are gated to the low-to-high transition of a port clock by enable signals. the clocks for each port are in- dependent of one another and can be asynchronous or coin- cident. the enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. communication between each port may bypass the fifos via two mailbox registers. the mailbox registers ? width matches the selected port b bus width. each mailbox register has a flag (mbf1 and mbf2 ) to signal when new mail has been stored. two kinds of reset are available on the cy7c436x6: master reset and partial reset. master reset initializes the read and write pointers to the first location of the memory array, config- ures the fifo for big or little endian byte arrangement and selects serial flag programming, parallel flag programming, or one of the three possible default flag offset settings, 8, 16, or 64. each fifo has its own independent master reset pin, mrs1 and mrs2. partial reset also sets the read and write pointers to the first location of the memory. unlike master reset, any settings ex- isting prior to partial reset (i.e., programming method and par- tial flag default offsets) are retained. partial reset is useful since it permits flushing of the fifo memory without changing any configuration settings. each fifo has its own, indepen- dent partial reset pin, prs1 and prs2 . the cy7c436x6 have two modes of operation: in the cy standard mode, the first word written to an empty fifo is de- posited into the memory array. a read operation is required to access that word (along with all other words residing in mem- ory). in the first-word fall-through mode (fwft), the first long-word (36-bit-wide) written to an empty fifo appears au- tomatically on the outputs, no read operation required (never- theless, accessing subsequent words does necessitate a for- mal read request). the state of the be/fwft pin during fifo operation determines the mode in use. each fifo has a combined empty/output ready flag (efa / ora and efb /orb) and a combined full/input ready flag (ffa /ira and ffc /irc). the ef and ff functions are select- ed in the cy standard mode. ef indicates whether the mem- ory is full or not. the ir and or functions are selected in the first-word fall-through mode. ir indicates whether or not the fifo has available memory locations. or shows whether the fifo has data available for reading or not. it marks the pres- ence of valid data on the outputs. (see footnote #24) each fifo has a programmable almost empty flag (aea and aeb ) and a programmable almost full flag (afa and afc ). aea and aeb indicate when a selected number of words writ- ten to fifo memory achieve a predetermined ? almost empty state. ? afa and afc indicate when a selected number of words written to the memory achieve a predetermined ? almost full state. ? (see footnote #47) ira, irc, afa , and afc are synchronized to the port clock that writes data into its array. ora, orb, aea , and aeb are synchronized to the port clock that reads data from its array. programmable offset for aea , aeb , afa , and afc are loaded in parallel using port a or in serial via the sd input. three default offset settings are also provided. the aea and aeb threshold can be set at 8, 16, or 64 locations from the empty boundary and afa and afc threshold can be set at 8, 16, or 64 locations from the full boundary. all these choices are made using the fs0 and fs1 inputs during master reset. two or more devices may be used in parallel to create wider data paths. such a width expansion requires no additional ex- ternal components. if at any time the fifo is not actively performing a function, the chip will automatically power down. during the power-down state, supply current consumption (i cc ) is at a minimum. initi- ating any operation (by activating control inputs) w ill immedi- ately take the device out of the power-down state. the cy7c436x6 are characterized for operation from 0 c to 70 c commercial, and from ? 40 c to 85 c industrial. input esd protection is greater than 2001v, and latch-up is prevented by the use of guard rings. selection guide cy7c43646/66/86 -7 cy7c43646/66/86 -10 cy7c43646/66/86 -15 maximum frequency (mhz) 133 100 66.7 maximum access time (ns) 6 8 10 minimum cycle time (ns) 7.5 10 15 minimum data or enable set-up (ns) 3 4 5 minimum data or enable hold (ns) 0 0 0 maximum flag delay (ns) 6 8 8 active power supply current (i cc1 ) (ma) commercial 100 100 100 industrial 100 cy7c43646 cy7c43666 cy7c43686 density 1k x 36 4k x 36 16k x 36 package 128 tqfp 128 tqfp 128 tqfp
cy7c43646 cy7c43666 cy7c43686 4 pin definitions signal name description i/o function a 0 ? 35 port a data i/o 36-bit bidirectional data port for side a. aea port a almost empty flag o programmable almost empty flag synchronized to clka. it is low when the number of words in fifo2 is less than or equal to the value in the almost empty a offset register, x2. (see footnote #47.) aeb port b almost empty flag o programmable almost empty flag synchronized to clkb. it is low when the number of words in fifo1 is less than or equal to the value in the almost empty b offset register, x1. (see footnote #47.) afa port a almost full flag o programmable almost full flag synchronized to clka. it is low when the number of empty locations in fifo1 is less than or equal to the value in the almost full a offset register, y1. (see footnote #47.) afc port c almost full flag o programmable almost full flag synchronized to clkc. it is low when the number of empty locations in fifo2 is less than or equal to the value in the almost full b offset register, y2. (see footnote #47.) b 0 ? 17 port b data o 18-bit output data port for port b. be/fwft big endian/ first-word fall- through select i this is a dual-purpose pin. during master reset, a high on be will select big endian operation. in this case, depending on the bus size, the most significant byte or word on port a is transferred to port b first for a-to-b data flow. for data flowing from port c to port a, the first word/byte written to port c will come out as the most significant word/ byte on port a. on the other hand a low on be will select little endian operation. in this case, the least significant byte or word on port a is transferred to port b first for a to b data flow. similarly, the first word/byte written into port c will come out as the least significant word/byte on port a for c-to-a data flow. after master reset, this pin selects the timing mode. a high on fwft selects cy standard mode, a low selects first- word fall-through mode. once the timing mode has been selected, the level on this pin must be static throughout device operation. c 0 ? 17 port b data i 18-bit input data port for port c. clka port a clock i clka is a continuous clock that synchronizes all data transfers through port a and can be asynchronous or coincident to clkb. ffa /ira, efa /ora, afa , and aea are all synchronized to the low-to-high transition of clka. clkb port b clock i clkb is a continuous clock that synchronizes all data transfers through port b and can be asynchronous or coincident to clka. efb /orb and aeb are all synchronized to the low-to-high transition of clkb. clkc port c clock i clkc is a continuous clock that synchronizes all data transfers through port c and can be asynchronous or coincident to clka. ffc /irc, and afc are all synchronized to the low-to-high transition of clkc. csa port a chip select icsa must be low to enable a low-to high transition of clka to read or write on port a. the a 0 ? 35 outputs are in the high-impedance state when csa is high. csb port b chip select icsb must be low to enable a low-to high transition of clkb to read or write on port b. the b 0 ? 17 outputs are in the high-impedance state when csb is high. efa /ora port a empty/ output ready flag o this is a dual-function pin. in the cy standard mode, the efa function is selected. efa indicates whether or not the fifo2 memory is empty. in the fwft mode, the ora function is selected. ora indicates the presence of valid data on a 0 ? 35 outputs, avail- able for reading. efa /ora is synchronized to the low-to-high transition of clka. (see footnote #24.) efb /orb port b empty/output ready flag o this is a dual-function pin. in the cy standard mode, the efb function is selected. efb indicates whether or not the fifo1 memory is empty. in the fwft mode, the orb function is selected. orb indicates the presence of valid data on b 0 ? 17 outputs, avail- able for reading. efb /orb is synchronized to the low-to-high transition of clkb. (see footnote #24.) ena port a enable i ena must be high to enable a low-to-high transition of clka to read or write data on port a. enb port b enable i enb must be high to enable a low-to-high transition of clkb to read or write data on port b.
cy7c43646 cy7c43666 cy7c43686 5 ffa /ira port a full/input ready flag o this is a dual-function pin. in the cy standard mode, the ffa function is selected. ffa indicates whether or not the fifo1 memory is full. in the fwft mode, the ira function is selected. ira indicates whether or not there is space available for writing to the fifo1 memory. ffa /ira is synchronized to the low-to-high transition of clka. ffc /irc port c full/input ready flag o this is a dual-function pin. in the cy standard mode, the ffc function is selected. ffc indicates whether or not the fifo2 memory is full. in the fwft mode, the irc function is selected. irc indicates whether or not there is space available for writing to the fifo2 memory. ffc /irc is synchronized to the low-to-high transition of clkb. fs1/sen flag offset select 1/serial enable i fs1/sen and fs0/sd are dual-purpose inputs used for flag offset register program- ming. during master reset, fs1/sen and fs0/sd, together with spm , select the flag offset programming method. three offset register programming methods are available: automatically load one of three preset values (8, 16, or 64), parallel load from port a, or serial load. when serial load is selected for flag offset register programming, fs1/ sen is used as an enable synchronous to the low-to-high transition of clka. when fs1/sen is low, a rising edge on clka load the bit present on fs0/sd into the x and y registers. the number of bit writes required to program the offset registers is 32 for the cy7c43626, 36 for the cy7c43636, 40 for the cy7c43646, 48 for the cy7c43666, and 56 for the cy7c43686. the first bit write stores the y-register msb and the last bit write stores the x-register lsb. fs0/sd flag offset select 0/serial data i mba port a mailbox select i a high level on mba chooses a mailbox register for a port a read or write operation. when a read operation is performed on port a, a high level on mba selects data from the mail2 register for output and a low level selects fifo2 output register data for output. when a write operation is performed on port a, a high level on mba will write the data into mail 1 register, while a low level will write the data into fifo 1. mbb port b mailbox select i a high level on mbb chooses a mailbox register for a port b read operation. when a read operation is performed on port b, a high level on mbb selects data from the mail1 register for output and a low level selects fifo1 output register data for output. mbc port c mailbox select i when a write operation is performed on port c, a high level on mbc writes data into mail2 register, and a low level writes into fifo2. mbf1 mail1 register flag ombf1 is set low by a low-to-high transition of clka that writes data to the mail1 register. writes to the mail1 register are inhibited while mbf1 is low. mbf1 is set high by a low-to-high transition of clkb when a port b read is selected and mbb is high. mbf1 is set high following either a master or partial reset of fifo1. mbf2 mail2 register flag ombf2 is set low by a low-to-high transition of clkb that writes data to the mail2 register. writes to the mail2 register are inhibited while mbf2 is low. mbf2 is set high by a low-to-high transition of clka when a port a read is selected and mba is high. mbf2 is set high following either a master or partial reset of fifo2. mrs1 fifo1 master reset i a low on this pin initializes the fifo1 read and write pointers to the first location of memory and sets the port b output register to all zeroes. a low pulse on mrs1 selects the programming method (serial or parallel) and one of three programmable flag default offsets for fifo1. it also configures port b for bus size and endian arrangement. four low-to-high transitions of clka and four low-to-high transitions of clkb must occur while mrs1 is low. mrs2 fifo2 master reset i a low on this pin initializes the fifo2 read and write pointers to the first location of memory and sets the port a output register to all zeroes. a low pulse on mrs2 selects one of three programmable flag default offsets for fifo2. four low-to-high transi- tions of clka and four low-to-high transitions of clkb must occur while mrs2 is low. prs1 fifo1 partial reset i a low on this pin initializes the fifo1 read and write pointers to the first location of memory and sets the port b output register to all zeroes. during partial reset, the currently selected bus size, endian arrangement, programming method (serial or par- allel), and programmable flag settings are all retained. prs2 fifo2 partial reset i a low on this pin initializes the fifo2 read and write pointers to the first location of memory and sets the port a output register to all zeroes. during partial reset, the currently selected bus size, endian arrangement, programming method (serial or par- allel), and programmable flag settings are all retained. pin definitions (continued) signal name description i/o function
cy7c43646 cy7c43666 cy7c43686 6 maximum ratings [1] (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ....................................... ? 65 c to +150 c ambient temperature with power applied .................................................... ? 55 c to +125 c supply voltage to ground potential ..................? 0.5v to +7.0v dc voltage applied to outputs in high z state [2] ..........................................? 0.5v to v cc +0.5v dc input voltage [2] .......................................? 0.5v to v cc +0.5v output current into outputs (low) ............................. 20 ma static discharge voltage ........................................... >2001v (per mil-std-883, method 3015) latch-up current ...................................................... >200ma notes: 1. stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute- maximum-rated conditions for extended periods may affect device reliability. 2. the input and output voltage ratings may be exceeded provided the input and output current ratings are observed. 3. operating v cc range for -7 speed is 5.0v 0.25v. renb port b read enable i renb must be high to enable a low-to-high transition of clkb to read data on port b. rt1 fifo1 retransmit i a low strobe on this pin will retransmit data on fifo1. this is achieved by bringing the read pointer back to location zero. the user will still need to perform read operations to retransmit the data. retransmit function applies to cy standard mode only. rt2 fifo2 retransmit i a low strobe on this pin will retransmit data on fifo2. this is achieved by bringing the read pointer back to location zero. the user will still need to perform read operations to retransmit the data. retransmit function applies to cy standard mode only. sizeb bus size select i a high on this pin when bm is high selects byte bus (9-bit) size on port b. a low on this pin when bm is high selects word (18-bit) bus size. sizeb works with bm and be to select the bus size and endian arrangement for port b. the level of sizeb must be static throughout device operation. sizec bus size select i a high on this pin when bm is high selects byte bus (9-bit) size on port c. a low on this pin when bm is high selects word (18-bit) bus size. sizec works with bm and be to select the bus size and endian arrangement for port b. the level of sizec must be static throughout device operation. spm serial programming i a low on this pin selects serial programming of partial flag offsets. a high on this pin selects parallel programming or default offsets (8, 16, or 64). w/ra port a write/ read select i a high selects a write operation and a low selects a read operation on port a for a low-to-high transition of clka. the a 0 ? 35 outputs are in the high-impedance state when w/ra is high. wenc port c write enable i wenc must be high to enable a low-to-high transition of clkc to write data on port c. pin definitions (continued) signal name description i/o function operating range range ambient temperature v cc [3] commercial 0 c to +70 c 5.0v0.5v industrial ? 40 c to +85 c 5.0v0.5v
cy7c43646 cy7c43666 cy7c43686 7 notes: 4. input signals switch from 0v to 3v with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 mhz, while data inputs switch at 10 mhz. outputs are unloaded. 5. all inputs = v cc ? 0.2v, except rclk and wclk (which are at frequency = 0 mhz). all outputs are unloaded. 6. tested initially and after any design or process changes that may affect these parameters. electrical characteristics over the operating range parameter description test conditions 7c43646/66/86 unit min. max. v oh output high voltage v cc = 4.5v., i oh = ? 4.0 ma 2.4 v v ol output low voltage v cc = 4.5v., i ol = 8.0 ma 0.5 v v ih input high voltage 2.0 v cc v v il input low voltage ? 0.5 0.8 v i ix input leakage current v cc = max. ? 10 +10 a i ozl i ozh output off, high z current v ss < v o < v cc ? 10 +10 a i cc1 [4] active power supply current com ? l 100 ma ind 100 ma i sb [5] average standby current com ? l 10 ma ind 10 ma capacitance [6] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 4 pf c out output capacitance 8 pf ac test loads and waveforms (-10 & -15) ac test loads and waveforms (-7) 3.0v 5v output r2=680 ? c l =30 pf including jig and scope gnd 90% 10% 90% 10% 3ns 3 ns all input pulses r1=1.1 k ? 3.0v gnd 90% 10% 90% 10% 3ns 3 ns all input pulses i/o 50 ? v cc /2 = ?
cy7c43646 cy7c43666 cy7c43686 8 switching characteristics over the operating range parameter description 7c43646/ 66/86 -7 7c43646/ 66/86 -10 7c43646/ 66/86 -15 unit min. max. min. max. min. max. f s clock frequency, clka,clkb, or clkc 133 100 67 mhz t clk clock cycle time, clka,clkb, or clkc 7.5 10 15 ns t clkh pulse duration, clka,clkb, or clkc high 3.5 4 6 ns t clkl pulse duration, clka,clkb, or clkc low 3.5 4 6 ns t ds set-up time, a 0 ? 35 before clka b 0 ? 17 before clkb , and c 0 ? 17 before clkc 3 4 5 ns t ens set-up time, csa , w/ra , ena, and mba before clka ; renb and mbb before clkb and wenc and mbc before clkc 3 4 5 ns t rsts set-up time, mrs1 , mrs2 , prs1 , or prs2 low before clka or clkb [7] 2.5 4 5 ns t fss set-up time, fs0 and fs1 before mrs1 and mrs2 high 6 7 7.5 ns t bes set-up time, be/fwft before mrs1 and mrs2 high 5 7 7.5 ns t spms set-up time, spm before mrs1 and mrs2 high 5 7 7.5 ns t sds set-up time, fs0/sd before clka 3 4 5 ns t sens set-up time, fs1/sen before clka 3 4 5 ns t fws set-up time, fwft before clka 0 0 0 ns t dh hold time, a 0 ? 35 before clka b 0 ? 17 before clkb , and c 0 ? 17 before clkc 0 0 0 ns t enh hold time, csa , w/ra , ena, and mba before clka renb and mbb before clkb and wenc and mbc before clkc 0 0 0 ns t rsth hold time, mrs1 , mrs2 , prs1 , or prs2 low after clka or clkb [7] 1 2 4 ns t fsh hold time, fs0 and fs1 after mrs1 and mrs2 high 1 1 2 ns t beh hold time, be/fwft after mrs1 and mrs2 high 1 1 2 ns t spmh hold time, spm after mrs1 and mrs2 high 1 1 2 ns t sdh hold time, fs0/sd after clka 0 0 0 ns t senh hold time, fs1/sen after clka 0 0 0 ns t sph hold time, fs1/sen high after mrs1 and mrs2 high 0 1 2 ns t skew1 [8] skew time between clka and clkb for efa / ora, efb /orb, ffa /ira, and ffc /irc 5 5 7.5 ns t skew2 [8] skew time between clka and clkb for aea , aeb , afa , afc 7 8 12 ns t a access time, clka to a 0 ? 35 and clkb to b 0 ? 17 1 6 1 8 3 10 ns t wff propagation delay time, clka to ffa /ira and clkb to ffc /irc 1 6 1 8 2 8 ns notes: 7. requirement to count the clock edge as one of at least four needed to reset a fifo. 8. skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship b etween clka cycle and clkb cycle.
cy7c43646 cy7c43666 cy7c43686 9 t ref propagation delay time, clka to efa/ora and clkb to efb /orb 1 6 1 8 1 8 ns t pa e propagation delay time, clka to aea and clkb to aeb 1 6 1 8 1 8 ns t pa f propagation delay time, clka to afa and clkc to afc 1 6 1 8 1 8 ns t pmf propagation delay time, clka to mbf1 low or mbf2 high and clkb to mbf2 low or mbf1 high 0 6 0 8 0 12 ns t pmr propagation delay time, clka to b 0 ? 17 [9] and clkb to a 0 ? 35 [10] 1 7 2 11 3 12 ns t mdv propagation delay time, mba to a 0 ? 35 valid and mbb to b 0 ? 17 valid 1 6 2 9 3 11 ns t rsf propagation delay time, mrs1 or prs1 low to aeb low, afa high, ffa /ira low, efb /orb low and mbf1 high and mrs2 or prs2 low to aea low, afc high, ffc /irc low, efa /ora low and mbf2 high 1 6 1 10 1 15 ns t en enable time, csa or w/ra low to a 0 ? 35 active and csb low and renb high to b 0 ? 17 active 1 5 2 8 2 10 ns t dis disable time, csa or w/ra high to a 0 ? 35 at high impedance and csb high or renb low to b 0 ? 17 at high impedance 1 5 1 6 1 8 ns t prt retransmit pulse width 60 60 60 ns t rtr retransmit recovery time 90 90 90 ns notes: 9. writing data to the mail1 register when the b 0 ? 17 outputs are active and mbb is high. 10. writing data to the mail2 register when the a 0 ? 35 outputs are active and mba is high. switching characteristics over the operating range (continued) parameter description 7c43646/ 66/86 -7 7c43646/ 66/86 -10 7c43646/ 66/86 -15 unit min. max. min. max. min. max.
cy7c43646 cy7c43666 cy7c43686 10 switching waveforms notes: 11. prs1 and mbc must be high during master reset until the rising edge of ffa /ira goes high. 12. if be/fwft is high, then efb /orb will go low one clkb cycle earlier than the case where be/fwft is low. fifo1 master reset loading x1 and y1 with a preset value of eight clka t rsf t rsf t rsf t wff t fss t fsh t spms t spmh t bes t beh t rsth t rsts t fws clkb mrs1 be/fwft spm fs1/sen , fs0/sd ffa /ira efb /orb aeb afa mbf1 [11, 12] t rsf t rsf
cy7c43646 cy7c43666 cy7c43686 11 notes: 13. prs2 and mbc must be high during master reset until the rising edge of ffc /irc goes high. 14. if be/fwft is high, then efa /ora will go low one clka cycle earlier than the case where be/fwft is low. switching waveforms (continued) fifo2 master reset loading x1 and y1 with a preset value of eight clkc t rsf t rsf t rsf t wff t fss t fsh t spms t spmh t bes t beh t rsts t rsts t fws clka mrs2 be/fwft spm fs1/sen , fs0,sd ffc /irc efa /ora aea afc mbf2 [13, 14] t rsf t rsf
cy7c43646 cy7c43666 cy7c43686 12 notes: 15. mrs1 must be high during partial reset. 16. mrs2 must be high during partial reset. switching waveforms (continued) fifo1 partial reset (cy standard and fwft modes) t rsf t rsf t rsf t rsts t rsth clka clkb prs1 ffa /ira efb /orb aeb afa mbf1 [12, 15] t wff t rsf t rsf fifo2 partial reset (cy standard and fwft modes) t rsf t rsf t rsf t rsts t rsth clkc clka prs2 ffc /irc efa /ora aea afc mbf1 [14, 16] t wff t rsf t rsf
cy7c43646 cy7c43666 cy7c43686 13 notes: 17. csa =low, w/ra =high, mba=low. it is not necessary to program offset register on consecutive clock cycles. 18. t skew1 is the minimum time between the rising clka edge and a rising clkb for ffc /irc to transition high in the next cycle. if the time between the rising edge of clka and rising edge of clkc is less than t skew1 , then ffc /irc may transition high one cycle later than shown. switching waveforms (continued) parallel programming of the almost-full flag and almost-empty flag offset values after reset (cy standard and fwft modes) t wff t fss t ds t fss t fsh t fsh t ens t enh t dh t skew1 [18] afa offset (y1) afc offset (y2) first word to fifo1 clka mrs1 , mrs2 spm fs1/sen , fs0/sd ffa/ ira ena a 0 ? 35 clkc ffc /irc [17] aeb offset (x1) aea offset (x2) t wff
cy7c43646 cy7c43666 cy7c43686 14 notes: 19. it is not necessary to program offset register bits on consecutive clock cycles. fifo write attempts are ignored until ira i s set high. 20. t skew1 is the minimum time between the rising clka edge and a rising clkc for ffc /irc to transition high in the next cycle. if the time between the rising edge of clka and rising edge of clkc is less than t skew1 , then ffc /irc may transition high one cycle later than show. 21. programmable offsets are written serially to the sd input in the order afa offset (y1), aeb offset (x1), afc offset (y2), and aea offset (x2). switching waveforms (continued) serial programming of the almost-full flag and almost-empty flag offset values (cy standard and fwft modes) t fss t sph t sens t senh t senh t sens t sdh t sds t sdh t sds t skew1 [20] t wff afa offset (y1) msb t fss t fsh t wff clka mrs1 , mrs2 spm ffa/ ira fs1/sen clkc ffc/ irc [19] fs0/sd [21] aea offset (x2) lsb
cy7c43646 cy7c43666 cy7c43686 15 note: 22. written to fifo1. switching waveforms (continued) t clkh t clkl t ens t enh t ens t enh t ens t enh t ens t enh t ds t dh t ens t enh t ens t enh high w1 [22] w2 [22] t clk clka ffa /ira csa w/ra mba ena a 0 ? 35 port a write cycle timing for fifo1 (cy standard and fwft modes) t ens t ens t enh t ens t enh t ds t dh t ens high t enh t enh clkc ffc /irc mbc wenc c 0 ? 17 port c word write cycle timing for fifo2 (cy standard and fwft modes)
cy7c43646 cy7c43666 cy7c43686 16 note: 23. unused bytes b 9 ? 17 contain all zeroes for byte-size reads. 24. when reading from the fifo under fwft, ora/orb signal should be included in the read logic to ensure proper operation. to re ad without gating the boundary flag (e.q. in bursts), use cy standard mode. switching waveforms (continued) port c byte write cycle timing for fifo2 (cy standard and fwft modes) t ens t enh t ens t enh t ds t dh t ens high t enh t enh clkc ffc /irc mbc wenc c 0 ? 8 25 t ens t enh t a t a t a t a t en t en t mdv t mdv t dis t a t a t a t a previous data read1 read1 read2 read2 read3 read3 read4 read4 read5 no operation high clkb efb /orb csb mbb renb b 0 ? 8 (standard mode) b 0 ? 8 (fwft mode) port b byte read cycle timing for fifo1 (cy standard and fwft modes) t dis [23, 24]
cy7c43646 cy7c43666 cy7c43686 17 note: 25. read from fifo2. switching waveforms (continued) 25 t dis t en t enh t a t a t a t a t en t en t mdv t mdv t dis previous data read 1 read 1 read 2 read 2 read 3 no operation clkb efb /orb csb mbb enb b 0 ? 17 (standard mode) b 0 ? 17 (fwft mode) port b word read cycle timing for fifo1 (cy standard and fwft modes) [24] 25 t clkh t clkl t ens t dis t ens t enh t clk t dis t enh t ens t enh t a t a t a t a t en t en t mdv t mdv w1 [25] w2 [25] w1 [25] w2 [25] w3 [25] previous no operation clka efa /ora csa w/ra mba ena a 0 ? 35 (standard mode) a 0 ? 35 (fwft mode) port a byte read cycle timing for fifo2 (cy standard and fwft modes) [24]
cy7c43646 cy7c43666 cy7c43686 18 notes: 26. if port b size is word or byte, orb is set low by the last word or byte read from fifo2, respectively. 27. t skew1 is the minimum time between a rising clka edge and a rising clkb edge for orb to transition high and to clock the next word to the fifo1 output register in three clkb cycles. if the time between the rising clka edge and rising clkb edge is less than t skew1 , then the transition of orb high and load of the first word to the output register may occur one clkb cycle later than shown. switching waveforms (continued) t clkh t clkl t ens t clk t enh t ens t enh t a t ds w1 low t dh high high fifo1 empty low low old data in fifo1 output register w1 t ens t enh t ref t ref t clkh t clkl t clk t skew1 [27] clka csa w/ra mba ena ffa /ira a 0 ? 35 clkb efb /orb csb mbb renb b 0 ? 17 orb flag timing and first data word fall through when fifo1 is empty (fwft mode) [26]
cy7c43646 cy7c43666 cy7c43686 19 notes: 28. if port b size is word or byte, efb is set low by the last word or byte read from fifo1, respectively. 29. t skew1 is the minimum time between a rising clka edge and a rising clkb edge for efb to transition high in the next clkb cycle. if the time between the rising clka edge and rising clkb edge is less than t skew1 , then the transition of efb high may occur one clkb cycle later than shown. switching waveforms (continued) t clkh t clkl t ens t enh t ens t enh t a t ds w1 low t dh high high fifo1 empty low low w1 t ens t enh t ref t ref t clkh t clkl t clk t clk t skew1 [29] clka csa w/ra mba ena ffa /ira a 0 ? 35 clkb efb /orb csb mbb renb b 0 ? 17 efb flag timing and first data read fall through when fifo1 is empty (cy standard mode) [28]
cy7c43646 cy7c43666 cy7c43686 20 notes: 30. if port b size is word or byte, t skew1 is referenced to the rising clkc edge that writes the last word or byte of the long word, respectively. 31. t skew1 is the minimum time between a rising clkc edge and a rising clka edge for ora to transition high and to clock the next word to the fifo2 output register in three clka cycles. if the time between the rising clkc edge and rising clka edge is less than t skew1 , then the transition of ora high and load of the first word to the output register may occur one clka cycle later than shown. switching waveforms (continued) t clkh t clkl t a w1 t dh high fifo2 empty low low low old data in fifo2 output register w1 t ens t enh t ref t ref t clkh t clkl t clk t skew1 [31] t clk t ds clkc wenc ffc /irc c 0 ? 17 clka efa /ora csa w/ra mba ena a 0 ? 35 ora flag timing and first data word fall through when fifo2 is empty (fwft mode) [30] mbc t enh t ens t enh t ens
cy7c43646 cy7c43666 cy7c43686 21 notes: 32. if port c size is word or byte, t skew1 is referenced to the rising clkc edge that writes the last word or byte of the long word, respectively. 33. t skew1 is the minimum time between a rising clkc edge and a rising clka edge for efa to transition high in the next clka cycle. if the time between the rising clkc edge and rising clka edge is less than t skew1 , then the transition of efa high may occur one clka cycle later than shown. switching waveforms (continued) efa flag timing and first data read when fifo2 is empty (cy standard mode) t clkh t clkl t ens t enh t ens t enh t a t ds w1 t dh high fifo2 empty low low low w1 t ens t enh t ref t ref t clkh t clkl t clk t clk t skew1 [33] clkc mbc wenc ffc /irc c 0 ? 17 clka efa /ira csa w/ra mba ena a 0 ? 35 [32]
cy7c43646 cy7c43666 cy7c43686 22 notes: 34. if port b size is word or byte, t skew1 is referenced to the rising clkb edge that reads the last word or byte write of the long word, respectively. 35. t skew1 is the minimum time between a rising clkb edge and a rising clka edge for ira to transition high in the next clka cycle. if th e time between the rising clkb edge and rising clka edge is less than t skew1 , then ira may transition high one clka cycle later than shown. switching waveforms (continued) t clkh t clkl t ens t enh t a low high fifo1 full low high t ens t enh t wff t wff t clkh t clkl t clk t clk t skew1 [35] t dh t ds t enh t ens previous word in fifo1 output register next word from fifo1 to fifo1 clkb csb mbb renb efb /orb b 0 ? 17 clka ffa /ira csa w/ra mba ena a 0 ? 35 ira flag timing and first available write when fifo1 is full (fwft mode) [34] low
cy7c43646 cy7c43666 cy7c43686 23 note: 36. t skew1 is the minimum time between a rising clkb edge and a rising clka edge for ffa to transition high in the next clka cycle. if the time between the rising clkb edge and rising clka edge is less than t skew1 , then the transition of ffa high may occur one clka cycle later than shown. switching waveforms (continued) t clkh t clkl t en t enh t a low high low high t ens t enh t wff t wff t clkh t clkl t clk t clk t skew1 [36] t dh t ds t enh t ens previous word in fifo1 output register next word from fifo1 clkb csb mbb enb efb /orb b 0 ? 17 clka ffa /ira csa w/ra mba ena a 0 ? 35 ffa flag timing and first available write when fifo1 is full (cy standard mode) [34] fifo1 full low
cy7c43646 cy7c43666 cy7c43686 24 notes: 37. if port c size is word or byte, irc is set low by the last word or byte write of the long word, respectively. 38. t skew1 is the minimum time between a rising clka edge and a rising clkc edge for irc to transition high in the next clkb cycle. if th e time between the rising clka edge and rising clkc edge is less than t skew1 , then the transition of irc high may occur one clkc cycle later than shown. switching waveforms (continued) t clkh t clkl t ens t enh t a low low high fifo2 full t ens t enh t wff t wff t clkh t clkl t clk t clk t skew1 [38] t dh t ds t enh t ens previous word in fifo2 output register next word from fifo2 to fifo2 low clka csa w/ra mba ena efa /ora a 0 ? 35 clkc ffc /irc mbc wenc c 0 ? 17 irc flag timing and first available write when fifo2 is full (fwft mode) [37]
cy7c43646 cy7c43666 cy7c43686 25 notes: 39. if port c size is word or byte, ffc is set low by the last word or byte write of the long word, respectively. 40. t skew1 is the minimum time between a rising clka edge and a rising clkb edge for ffc to transition high in the next clkb cycle. if the time between the rising clka edge and rising clkc edge is less than t skew1 , then the transition of ffc high may occur one clkc cycle later than shown. switching waveforms (continued) t clkh t clkl t ens t enh t a low low high fifo2 full t ens t enh t wff t wff t clkh t clkl t clk t clk t skew1 [40] t dh t ds t enh t ens previous word in fifo2 output register next word from fifo2 to fifo2 low clka csa w/ra mba ena efa /ora a 0 ? 35 clkc ffc /irc mbc wenc c 0 ? 17 ffc flag timing and first available write when fifo2 is full (cy standard mode) [39]
cy7c43646 cy7c43666 cy7c43686 26 notes: 41. fifo1 write (csa = low, w/ra = low, mba = low), fifo1 read (csb = low, w /rb = high, mbb = low). data in the fifo1 output register has been read from the fifo. 42. if port b size is word or byte, aeb is set low by the last word or byte read from fifo1, respectively. 43. t skew2 is the minimum time between a rising clka edge and a rising clkb edge for aeb to transition high in the next clkb cycle. if the time between the rising clka edge and rising clkb edge is less than t skew2 , then aeb may transition high one clkb cycle later than shown. 44. fifo2 write (mbb = low), fifo2 read (csa = low, w/ra = low, mba = low). data in the fifo2 output register has been read from the fifo. 45. if port c size is word or byte, t skew2 is referenced to the rising clkc edge that writes the last word or byte of the long word, respectively. 46. t skew2 is the minimum time between a rising clkc edge and a rising clka edge for aea to transition high in the next clka cycle. if the time between the rising clkc edge and rising clka edge is less than t skew2 , then aea may transition high one clka cycle later than shown. 47. when fifo is operated at the almost empty/full boundary, there may be an uncertainty of up to 3 clock cycles for flag assert ion and deassertion. refer to ? designing with cy7c436xx synchronous fifo ? application notes for more details on flag uncertainties. switching waveforms (continued) clka ena clkb aeb renb timing for aeb when fifo2 is almost empty (cy standard and fwft modes) [41, 42, 47] clkc wenc clka aea ena timing for aea when fifo2 is almost empty (cy standard and fwft modes) [44, 45, 47] t pae t pae t enh t ens t skew2 [46] t ens t enh x2 word in fifo2 (x2+1) words in fifo2 t pae t pae t enh t ens t skew2 [43] t ens t enh x1 word in fifo1 (x1+1)words in fifo2
cy7c43646 cy7c43666 cy7c43686 27 notes: 48. fifo1 write (csa = low, w/ra = high, mba = low), fifo1 read (csb = low, mbb = low). data in the fifo1 output register has been read from the fifo. 49. d = maximum fifo depth = 1k for the cy7c43646, 4k for the cy7c43666, and 16k for the cy7c43686. 50. if port b size is word or byte, t skew2 is referenced to the rising clkb edge that writes the last word or byte of the long word, respectively. 51. t skew2 is the minimum time between a rising clka edge and a rising clkb edge for afa to transition high in the next clka cycle. if the time between the rising clka edge and rising clkb edge is less than t skew2 , then afa may transition high one clkb cycle later than shown. 52. if port c size is word or byte, afc is set low by the last word or byte write of the long word, respectively. 53. t skew2 is the minimum time between a rising clkc edge and a rising clka edge for afc to transition high in the next clkc cycle. if the time between the rising clkc edge and rising clka edge is less than t skew2 , then afc may transition high one clka cycle later than shown. switching waveforms (continued) timing for afa when fifo1 is almost full (cy standard and fwft modes) clka ena afa clkb renb [47, 48, 49, 50] t paf t enh t ens t paf t ens t enh [d ? (y1+1)] words in fifo1 (d ? y1)words in fifo1 t skew2 [51] clkc wenc afc clka ena timing for afc when fifo2 is almost full (cy standard and fwft modes) [44, 47, 49, 52] t paf t enh t ens t paf t ens t enh [d ? (y2+1)] words in fifo2 (d ? y2)words in fifo2 t skew2 [53]
cy7c43646 cy7c43666 cy7c43686 28 note: 54. if port b is configured for word size, data can be written to the mail1 register using a 0 ? 17 (a 18 ? 35 are ? don ? t care ? inputs). in this first case b 0 ? 17 will have valid data). if port b is configured for byte size, data can be written to the mail1 register using a 0 ? 8 (a 9 ? 35 are ? don ? t care ? inputs). in this second case, b 0 ? 8 will have valid data (b 9 ? 17 will be indeterminate). switching waveforms (continued) t enh t ens t enh t ens t enh t ens t enh t ens t dh t ds w1 t pmf t pmf t en t mdv t pmr t ens t enh t dis fifo1 output register w1 (remains valid in mail1 register after read) clka csa w/ra mba ena a 0 ? 35 clkb mbf1 csb mbb renb timing for mail1 register and mbf1 flag (cy standard and fwft modes) [54] b 0 ? 17
cy7c43646 cy7c43666 cy7c43686 29 notes: 55. if port c is configured for word size, data can be written to the mail2 register using c 0 ? 17 . in this first case a 0 ? 17 will have valid data (a 18 ? 35 will be indeterminate). if port c is configured for byte size, data can be written to the mail2 register using b 0 ? 8 (b 9 ? 17 are ? don ? t care ? inputs). in this second case, a 0 ? 8 will have valid data (a 9 ? 35 will be indeterminate). 56. retransmit is performed in the same manner for fifo2. 57. clocks are free-running in this case. cy standard mode only. 58. the flags may change state during retransmit as a result of the offset of the read and write pointers, but flags will be val id at t rt r . 59. for the af & ae flags, two clock cycles are necessary after t rtr to update these flags. switching waveforms (continued) t enh t ens t dh t ds w1 t pmf t pmf t en t mdv t pmr t ens t enh t dis fifo2 output register w1 (remains valid in mail2 register after read) clkc mbc wenc c 0 ? 17 clka mbf2 csa w/ra mba ena a 0 ? 35 timing for mail2 register and mbf2 flag (cy standard and fwft modes) [55] fifo1 retransmit timing renb rt1 t prt t rtr ef b /ffa [56, 57, 58, 59]
cy7c43646 cy7c43666 cy7c43686 30 signal description master reset ( 056 , 056 ) each of the two fifo memories of the cy7c436x6 undergoes a complete reset by taking its associated master reset (mrs1 , mrs2 ) input low for at least four port a clock (clka) and four port b clock (clkb) low-to-high transitions. the master reset inputs can switch asynchronously to the clocks. a master reset initializes the internal read and write pointers and forces the full/input ready flag (ffa /ira, ffc /irc) low, the empty/output ready flag (efa /ora, efb /orb) low, the almost empty flag (aea , aeb ) low, and the almost full flag (afa , afc ) high. a master reset also forces the mailbox flag (mbf1 , mbf2 ) of the parallel mailbox register high. after a master reset, the fifo ? s full/input ready flag is set high after two clock cycles to begin normal operation. a master re- set must be performed on the fifo after power-up, before data is written to its memory. a low-to-high transition on a fifo master reset (mrs1 , mrs2 ) input latches the value of the big endian (be) input or determines the order by which bytes are transferred through por t b. a low-to-high transition on a fifo reset (mrs1 , mrs2 ) input latches the values of the flag select (fs0, fs1) and se- rial programming mode (spm ) inputs for choosing the almost full and almost empty offset programming method (see al- most empty and almost full flag offset programming below). partial reset ( 356 , 356 ) each of the two fifo memories of the cy7c436x6 undergoes a limited reset by taking its associated partial reset (prs1 , prs2 ) input low for at least four port a clock (clka) and four port b clock (clkb) low-to-high transitions. the partial re- set inputs can switch asynchronously to the clocks. a partial reset initializes the internal read and write pointers and forces the full/input ready flag (ffa /ira, ffc /irc) low, the emp- ty/output ready flag (efa /ora, efb /orb) low, the almost empty flag (aea , aeb ) low, and the almost full flag (afa , afc ) high. a partial reset also forces the mailbox flag (mbf1 , mbf2 ) of the parallel mailbox register high. after a partial reset, the fifo ? s full/input ready flag is set high after two clock cycles to begin normal operation. whatever flag offsets, programming method (parallel or serial), and timing mode (fwft or cy standard mode) are currently selected at the time a partial reset is initiated, those settings will remain unchanged upon completion of the reset operation. a partial reset may be useful in the case where reprogram- ming a fifo following a master reset would be inconvenient. big endian/first-word fall-through (be/fwft ) this is a dual-purpose pin. at the time of master reset, the be select function is active, permitting a choice of big or little endian byte arrangement for data written to or read from port b. this selection determines the order by which bytes (or words) of data are transferred through this port. for the follow- ing illustrations, assume that a byte (or word) bus size has been selected for port b. (note that when port b is configured for a long-word size, the big endian function has no application and the be input is a ? don ? t care. ? ) a high on the be/fwft input when the master reset (mrs1 and mrs2 ) inputs go from low to high will select a big en- dian arrangement. when data is moving in the direction from port a to port b, the most significant byte (word) of the long- word written to port a will be transferred to port b first; the least significant byte (word) of the long-word written to port a will be transferred to port b last. when data is moving in the direction from port c to port a, the byte (word) written to port c first will be transferred to port a as the most significant byte (word) of the long-word; the byte (word) written to port c last will be transferred to port a as the least significant byte (word) of the long- word. a low on the be/fwft input when the master reset (mrs1 and mrs2 ) inputs go from low to high will select a little endian arrangement. when data is moving in the direction from port a to port b, the least significant byte (word) of the long-word written to port a will be transferred to port b first; the most significant byte (word) of the long-word written to port a will be transferred to port b last. when data is moving in the direction from port c to port a, the byte (word) written to port c first will be transferred to port a as the least significant byte (word) of the long-word; the byte (word) written to port c last will be transferred to port a as the most significant byte (word) of the long- word. after master reset, the fwft select function is active, permit- ting a choice between two possible timing modes: cy stan- dard mode or first-word fall-through (fwft) mode. once the master reset (mrs1 , mrs2 ) input is high, a high on the be/fwft input during the next low-to-high transition of clka (for fifo1) and clkb (for fifo2) will select cy stan- dard mode. this mode uses the empty flag function (efa , efb ) to indicate whether or not there are any words present in the fifo memory. it uses the full flag function (ffa , ffc ) to indicate whether or not the fifo memory has any free space for writing. in cy standard mode, every word read from the fifo, including the first, must be requested using a formal read operation. once the master reset (mrs1 , mrs2 ) input is high, a low on the be/fwft input at the second low-to-high transition of clka (for fifo1) and clkc (for fifo2) will select fwft mode. this mode uses the output ready function (ora, orb) to indicate whether or not there is valid data at the data outputs (a 0 ? 35 or b 0 ? 17 ). it also uses the input ready function (ira, irc) to indicate whether or not the fifo memory has any free space for writing. in the fwft mode, the first word written to an empty fifo goes directly to data outputs, no read request necessary. subsequent words must be accessed by performing a formal read operation. following master reset, the level applied to the be/fwft in- put to choose the desired timing mode must remain static throughout the fifo operation. programming the almost empty and almost full flags four registers in the cy7c436x6 are used to hold the offset values for the almost empty and almost full flags. the port b almost empty flag (aeb ) offset register is labeled x1 and the port a almost empty flag (aea ) offset register is labeled x2. the port a almost full flag (afa ) offset register is labeled y1 and the port c almost full flag (afc ) offset register is labeled y2. the index of each register name corresponds with preset values during the reset of a fifo, programmed in parallel us- ing the fifo ? s port a data inputs, or programmed in serial using the serial data (sd) input (see ta b l e 1 ). to load a fifo ? s almost empty flag and almost full flag offset registers with one of the three preset values listed in ta b l e 1 ,
cy7c43646 cy7c43666 cy7c43686 31 the serial program mode (spm ) and at least one of the flag- select inputs must be high during the low-to-high transition of its master reset input (mrs1 and mrs2 ). for example, to load the preset value of 64 into x1 and y1, spm , fs0, and fs1 must be high when fifo1 reset (mrs1 ) returns high. flag- offset registers associated with fifo2 are loaded with one of the preset values in the same way with master reset (mrs2 ). when using one of the preset values for the flag offsets, the fifos can be reset simultaneously or at different times. to program the x1, x2, y1, and y2 registers from port a, per- form a master reset on both fifos simultaneously with spm high and fs0 and fs1 low during the low-to-high transi- tion of mrs1 and mrs2 . after this reset is complete, the first four writes to fifo1 do not store data in ram but load the offset registers in the order y1, x1, y2, x2. the port a data inputs used by the offset registers are (a 0 ? 9 ), (a 0 ? 11 ), or (a 0 ? 13 ), for the cy7c436x6, respectively. the highest num- bered input is used as the most significant bit of the binary number in each case. valid programming values for the regis- ters range from 0 to 1023 for the cy7c43646; 1 to 4095 for the cy7c43666; 0to 16383 for the cy7c43686. after all the offset registers are programmed from port a, the port c full/input ready (ffc /irc) is set high and both fifos begin normal operation. to program the x1, x2, y1, and y2 registers serially, initiate a master reset with spm low, fs0/sd low and fs1/sen high during the low-to-high transition of mrs1 and mrs2 . after this reset is complete, the x and y register values are loaded bit-wise through the fs0/sd input on each low-to- high transition of clka that the fs1/sen input is low. 40, 48, or 56 bit writes are needed to complete the programming for the cy7c436x6, respectively. the four registers are written in the order y1, x1, y2, and, finally, x2. the first-bit write stores the most significant bit of the y1 register and the last- bit write stores the least significant bit of the x2 register. each register value can be programmed from 0 to 1023 (cy7c43646), 0 to 4095 (cy7c43666), or 0 to 16383 (cy7c43686). when the option to program the offset registers serially is cho- sen, the port a full/input ready (ffa /ira) flag remains low until all register bits are written. ffa /ira is set high by the low-to-high transition of clka after the last bit is loaded to allow normal fifo1 operation. the port c full/input ready (ffc /irc) flag also remains low throughout the serial pro- gramming process, until all register bits are written. ffc /irc is set high by the low-to-high transition of clkc after the last bit is loaded to allow normal fifo2 operation. spm , fs0/sd, and fs1/sen function the same way in both cy standard and fwft modes. fifo write/read operation the state of the port a data (a 0 ? 35 ) lines is controlled by port a chip select (csa ) and port a write/read select (w/ra ). the a 0 ? 35 lines are in the high-impedance state when either csa or w/ra is high. the a 0 ? 35 lines are active outputs when both csa and w/ra are low. data is loaded into fifo1 from the a 0 ? 35 inputs on a low-to- high transition of clka when csa is low, w/ra is high, ena is high, mba is low, and ffa /ira is high. data is read from fifo2 to the a 0 ? 35 outputs by a low-to-high transition of clka when csa is low, w/ra is low, ena is high, mba is low, and efa /ora is high (see ta b l e 2 ). fifo reads and writes on port a are independent of any concurrent port b operation. the state of the port b data (b 0 ? 17 ) lines is controlled by the port b chip select (csb ) and port b read select (renb). the b 0 ? 17 lines are in the high-impedance state when either csb is high or renb is low. the b 0 ? 17 lines are active outputs when csb is low and renb is high. data is loaded into fifo2 from the c 0 ? 17 inputs on a low-to- high transition of clkc when wenc is low, mbc is low, and ffc /irc is high. data is read from fifo1 to the b 0 ? 17 outputs by a low-to-high transition of clkb when csb is low, renb is high, mbb is low, and efb /orb is high (see table 3 ). fifo reads on port b and writes to port c are independent of any concurrent port a operation. the set-up and hold time constraints to the port clocks for the port chip selects and write/read selects are only for enabling write and read operations and are not related to high-imped- ance control of the data outputs. if a port enable is low during a clock cycle, the port ? s chip select and write/read select may change states during the set-up and hold time window of the cycle. when operating the fifo in fwft mode with the output ready flag low, the next word written is automatically sent to the fifo ? s output register by the low-to-high transition of the port clock that sets the output ready flag high, data re- siding in the fifo ? s memory array is clocked to the output reg- ister only when a read is selected using the port ? s chip select, write/read select, enable, and mailbox select. when operating the fifo in cy standard mode, regardless of whether the empty flag is low or high, data residing in the fifo ? s memory array is clocked to the output register only when a read is selected using the port ? s chip select, write/ read select, enable, and mailbox select. synchronized fifo flags each fifo is synchronized to its port clock through at least two flip-flop stages. this is done to improve flag-signal reliabil- ity by reducing the probability of the metastable events when clka, clkb, and clkc operate asynchronously to one an- other. efa /ora, aea , ffa /ira, and afa are synchronized to clka. efb /orb and aeb are synchronized to clkb. ffc / irc and afc are synchronized to clkc. table 5 and table 6 show the relationship of each port flag to fifo1 and fifo2. empty/output ready flags (efa /ora, efb /orb) these are dual-purpose flags. in the fwft mode, the output ready (ora, orb) function is selected. when the output ready flag is high, new data is present in the fifo output register. when the output ready flag is low, the previous data word is present in the fifo output register and attempted fifo reads are ignored.(see footnote #24) in the cy standard mode, the empty flag (efa , efb ) function is selected. when the empty flag is high, data is available in the fifo ? s ram memory for reading to the output register. when empty flag is low, the previous data word is present in the fifo output register and attempted fifo reads are ig- nored. the empty/output ready flag of a fifo is synchronized to the port clock that reads data from its array. for both the fwft and cy standard modes, the fifo read pointer is increment- ed each time a new word is clocked to its output register. the
cy7c43646 cy7c43666 cy7c43686 32 state machine that controls an output ready flag monitors a write pointer and read pointer comparator that indicates when the fifo sram status is empty, empty+1, or empty+2. in fwft mode, from the time a word is written to a fifo, it can be shifted to the fifo output register in a minimum of three cycles of the output ready flag synchronizing clock. there- fore, an output ready flag is low if a word in memory is the next data to be sent to the fifo output register and three cy- cles have not elapsed since the time the word was written. the output ready flag of the fifo remains low until the third low-to-high transition of the synchronizing clock occurs, si- multaneously forcing the output ready flag high and shifting the word to the fifo output register. in the cy standard mode, from the time a word is written to a fifo, the empty flag will indicate the presence of data avail- able for reading in a minimum of two cycles of the empty flag synchronizing clock. therefore, an empty flag is low if a word in memory is the next data to be sent to the fifo output register and two cycles have not elapsed since the time the word was written. the empty flag of the fifo remains low until the second low-to-high transition of the synchronizing clock occurs, forcing the empty flag high; only then can data be read. a low-to-high transition on an empty/output ready flag synchronizing clock begins the first synchronization cycle of a write if the clock transition occurs at time t skew1 or greater after the write. otherwise, the subsequent clock cycle can be the first synchronization cycle. full/input ready flags (ffa /ira, ffc /irc) this is a dual-purpose flag. in fwft mode, the input ready (ira and irc) function is selected. in cy standard mode, the full flag (ffa and ffc ) function is selected. for both timing modes, when the full/input ready flag is high, a memory location is free in the sram to receive new data. no memory locations are free when the full/input ready flag is low and attempted writes to the fifo are ignored. the full/input ready flag of a fifo is synchronized to the port clock that writes data to its array. for both fwft and cy stan- dard modes, each time a word is written to a fifo, its write pointer is incremented. the state machine that controls a full/ input ready flag monitors a write pointer and read pointer comparator that indicates when the fifo sram status is full, full ? 1, or full ? 2. from the time a word is read from a fifo, its previous memory location is ready to be written to in a mini- mum of two cycles of the full/input ready flag synchronizing clock. therefore, an full/input ready flag is low if less than two cycles of the full/input ready flag synchronizing clock have elapsed since the next memory write location has been read. the second low-to-high transition on the full/input ready flag synchronizing clock after the read sets the full/ input ready flag high. a low-to-high transition on a full/input ready flag synchro- nizing clock begins the first synchronization cycle of a read if the clock transition occurs at time t skew1 or greater after the read. otherwise, the subsequent clock cycle can be the first synchronization cycle. almost empty flags (aea , aeb ) the almost empty flag of a fifo is synchronized to the port clock that reads data from its array. the state machine that controls an almost empty flag monitors a write pointer and read pointer comparator that indicates when the fifo sram status is almost empty, almost empty+1, or almost empty+2. the almost empty state is defined by the contents of register x1 for aeb and register x2 for aea . these registers are load- ed with preset values during a fifo reset, programmed from port a, or programmed serially (see almost empty flag and almost full flag offset programming above). an almost empty flag is low when its fifo contains x or less words and is high when its fifo contains (x+1) or more words. (see foot- note #47) two low-to-high transitions of the almost empty flag syn- chronizing clock are required after a fifo write for its almost empty flag to reflect the new level of fill. therefore, the almost empty flag of a fifo containing (x+1) or more words remains low if two cycles of its synchronizing clock have not elapsed since the write that filled the memory to the (x+1) level. an almost empty flag is set high by the second low-to-high transition of its synchronizing clock after the fifo write that fills memory to the (x+1) level. a low-to-high transition of an almost empty flag synchronizing clock begins the first syn- chronization cycle if it occurs at time t skew2 or greater after the write that fills the fifo to (x+1) words. otherwise, the sub- sequent synchronizing clock cycle may be the first synchroni- zation cycle. almost full flags (afa , afc ) the almost full flag of a fifo is synchronized to the port clock that writes data to its array. the state machine that controls an almost full flag monitors a write pointer and read pointer com- parator that indicates when the fifo sram status is almost full, almost full ? 1, or almost full ? 2. the almost full state is defined by the contents of register y1 for afa and register y2 for afc . these registers are loaded with preset values during a fifo reset, programmed from port a, or programmed seri- ally (see almost empty flag and almost full flag offset pro- gramming above). an almost full flag is low when the num- ber of words in its fifo is greater than or equal to (1024 ? y), (4096 ? y), or (16384 ? y) for the cy7c436x6 respectively. an almost full flag is high when the number of words in its fifo is less than or equal to [1024 ? (y+1)], [4096 ? (y+1)], or [16384 ? (y+1)] for the cy7c436x6 respectively. (see footnote #47) two low-to-high transitions of the almost full flag synchro- nizing clock are required after a fifo read for its almost full flag to reflect the new level of fill. therefore, the almost full flag of a fifo containing [1024/4096/16384 ? (y+1)] or less words remains low if two cycles of its synchronizing clock have not elapsed since the read that reduced the number of words in memory to [1024/4096/16384 ? (y+1)]. an almost full flag is set high by the second low-to-high transition of its synchronizing clock after the fifo read that reduces the num- ber of words in memory to [1024/4096/16384 ? (y+1)]. a low- to-high transition of an almost full flag synchronizing clock begins the first synchronization cycle if it occurs at time t skew2 or greater after the read that reduces the number of words in memory to [1024/4096/16384 ? (y+1)]. otherwise, the subse- quent synchronizing clock cycle may be the first synchroniza- tion cycle. mailbox registers each fifo has a 36-bit bypass register to pass command and control information between port a and port b/port c without putting it in queue. the mailbox select (mba, mbb, mbc) in-
cy7c43646 cy7c43666 cy7c43686 33 puts choose between a mail register and a fifo for a port data transfer operation. the usable width of both the mail1 and mail2 registers matches the selected bus size for port c. a low-to-high transition on clka writes a 0 ? 35 data to the mail1 register when a port a write is selected by csa , w/ra , and ena with mba high. when sending data from port c to port a via the mail2 register, the following is the case: a low-to-high transition on clkc writes c 0 ? 17 data to the mail2 register when a port c write is selected by wenc with mbc high. if the selected port c bus size is also 18 bits, then the usable width of the mail2 register employs data lines c 0 ? 17 . if the selected port c bus size is 9 bits, then the usable width of the mail2 register employs data lines c 0 ? 8 . (in this case, c 9 ? 17 are ? don ? t care ? inputs.) writing data to a mail register sets its corresponding flag (mbf1 or mbf2 ) low. attempted writes to a mail register are ignored while the mail flag is low. when data outputs of a port are active, the data on the bus comes from the fifo output register when the port mailbox select input is low and from the mail register when the port mailbox select input is high. the mail1 register flag (mbf1 ) is set high by a low-to- high transition on clkb when a port b read is selected by csb , renb, and enb with mbb high. for an 18-bit bus size, 18 bits of mailbox data are placed on b 0 ? 17 . for a 9-bit bus size, 9 bits of mailbox data are placed on b 0 ? 8 . (in this case, b 9 ? 17 are indeterminate.) the mail2 register flag (mbf2 ) is set high by a low-to- high transition on clka when a port a read is selected by csa , w/ra , and ena with mba high. the data in a mail register remains intact after it is read and changes only when new data is written to the register. the endian select feature has no effect on the mailbox data. bus sizing the port b and port c buses can be configured in a 18-bit word or 9-bit byte format for data read from fifo1 or written to fifo2. the levels applied to the port b bus size select (sizeb) and the port c bus size select (sizec) determine the width of the buses. the bus size can be selected independent- ly for ports b and c. these levels should be static throughout fifo operation. both bus size selections are implemented at the completion of master reset, by the time the full/input ready flag is set high. two different methods for sequencing data transfer are avail- able for port b when the bus size selection is either byte or word-size. they are referred to as big endian (most significant byte first) and little endian (least significant byte first). the level applied to the big endian select (be) input during the low-to-high transition of mrs1 and mrs2 selects the endi- an method that will be active during fifo operation. be is a ? don ? t care ? input when the bus size selected for port b is long- word. the endian method is implemented at the completion of master reset, by the time the full/input ready flag is set high. only 36-bit long-word data is written to or read from the two fifo memories on the cy7c436x6. bus-matching operations are done after data is read from the fifo1 ram and before data is written to fifo2 ram. these bus-matching operations are not available when transferring data via mailbox registers. furthermore, both the word- and byte-size bus selections limit the width of the data bus that can be used for mail register operations. in this case, only those byte lanes belonging to the selected word- or byte-size bus can carry mailbox data. the remaining data outputs will be indeterminate. the remaining data inputs will be ? don ? t care ? inputs. for example, when a word-size bus is selected, then mailbox data can be transmit- ted only between a 0 ? 17 and b 0 ? 17 . when a byte-size bus is selected, then mailbox data can be transmitted only between a 0 ? 8 and b 0 ? 8 . bus-matching fifo1 reads data is written to the fifo1 ram in 36-bit long-word incre- ments. if byte or word size is implemented on port b, only the first one or two bytes appear on the selected portion of the fifo1 output register, with the rest of the long-word stored in auxiliary registers. in this case, subsequent fifo1 reads out- put the rest of the long-word to the fifo1 output register. when reading data from fifo1 as byte, the unused b 9 ? 17 out- puts are indeterminate. bus-matching fifo2 writes data is written to the fifo2 ram in 18-bit word increments. data written to fifo2 with a byte or word bus size stores the initial bytes or words in auxiliary registers. the clkc rising edge that writes the word to fifo2 also stores the entire long- word in fifo2 ram. when reading data from fifo2 in byte format, the unused c 8 ? 17 outputs are low. retransmit (rt1 , rt2 ) the retransmit feature is beneficial when transferring packets of data. it enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. retransmit func- tion applies to cy standard mode only. the retransmit feature is intended for use when a number of writes equal to or less than the depth of the fifo have oc- curred and at least one word has been read since the last reset cycle. a low pulse on rt1 , (rt2) resets the internal read pointer to the first physical location of the fifo. clka and clkb may be free running but renb & (ena) must be dis- abled during and t rtr after the retransmit pulse. with every valid read cycle after retransmit, previously accessed data is read and the read pointer is incremented until it is equal to the write pointer. flags are governed by the relative locations of the read and write pointers and are updated during a retrans- mit cycle. data written to the fifo after activation of rt1 , (rt2) are transmitted also. the full depth of the fifo can be repeatedly retransmitted. .
cy7c43646 cy7c43666 cy7c43686 34 a b 9 ? 17 b b 0 ? 8 c b 9 ? 17 d b 0 ? 8 c d a b a b c d (a) word size ? big endian (b) word size ? little endian (c) byte size ? big endian %( 6,=(% +/ %( 6,=(% // %( 6,=(% ++ 1st: read from fifo1 2nd: read from fifo1 1st: read from fifo1 2nd: read from fifo1 1st: read from fifo1 2nd: read from fifo1 3rd: read from fifo1 4th: read from fifo1 byte order on port a: d c b a (d) byte size ? little endian %( 6,=(% /+ 1st: read from fifo1 2nd: read from fifo1 3rd: read from fifo1 4th: read from fifo1 port b bus sizing a a 27 ? 35 b a 18 ? 26 c a 9 ? 17 d a 0 ? 8 write to fifo1 b 9 ? 17 b 0 ? 8 b 9 ? 17 b 0 ? 8 b 9 ? 17 b 0 ? 8 b 9 ? 17 b 0 ? 8 b 9 ? 17 b 0 ? 8 b 9 ? 17 b 0 ? 8 b 9 ? 17 b 0 ? 8 b 9 ? 17 b 0 ? 8 b 9 ? 17 b 0 ? 8 b 9 ? 17 b 0 ? 8
cy7c43646 cy7c43666 cy7c43686 35 a c 9 ? 17 b c 0 ? 8 c c 9 ? 17 d c 0 ? 8 c d a b a b c d (a) word size ? big endian (b) word size ? little endian (c) byte size ? big endian %( 6,=(& +/ %( 6,=(& // %( 6,=(& ++ 1st: write to fifo2 2nd: write to fifo2 1st: write to fifo2 2nd: write to fifo2 1st: write to fifo2 2nd: write to fifo2 3rd: write to fifo2 4th: write to fifo2 d c b a (d) byte size ? little endian %( 6,=(& /+ 1st: write to fifo2 2nd: write to fifo2 3rd: write to fifo2 4th: write to fifo2 port c bus sizing byte order on port a: a a 27 ? 35 b a 18 ? 26 c a 9 ? 17 d a 0 ? 8 read from fifo2 c 9 ? 17 c 0 ? 8 c 9 ? 17 c 0 ? 8 c 9 ? 17 c 0 ? 8 c 9 ? 17 c 0 ? 8 c 9 ? 17 c 0 ? 8 c 9 ? 17 c 0 ? 8 c 9 ? 17 c 0 ? 8 c 9 ? 17 c 0 ? 8 c 9 ? 17 c 0 ? 8 c 9 ? 17 c 0 ? 8
cy7c43646 cy7c43666 cy7c43686 36 notes: 60. x1 register holds the offset for aeb ; y1 register holds the offset for afa . 61. x2 register holds the offset for aea ; y2 register holds the offset for afc . table 1. flag programming [47] spm fs1/sen fs0/sd mrs1 mrs2 x1 and y1 registers [60] x2 and y2 registers [61] h h h x 64 x h h h x x 64 h h l x 16 x h h l x x 16 h l h x 8 x h l h x x 8 h l l parallel programming via port a parallel programming via port a l h l serial programming via sd serial programming via sd l h h reserved reserved l l h reserved reserved l l l reserved reserved table 2. port a enable function table csa w/ra ena mba clka a 0 ? 35 outputs port function h x x x x in high-impedance state none l h l x x in high-impedance state none lh hl in high-impedance state fifo1 write lh hh in high-impedance state mail1 write l l l l x active, fifo2 output register none ll hl active, fifo2 output register fifo2 read l l l h x active, mail2 register none ll hh active, mail2 register mail2 read (set mbf2 high) table 3. port b enable function table csb renb mbb clkb b 0 ? 17 outputs port function h x x x in high-impedance state none l l l x active, fifo1 output register none lh l active, fifo1 output register fifo1 read l l h x active, mail1 register none lh h active, mail1 register mail1 read (set mbf1 high) table 4. port c enable function table wenc mbc clkc c 0 ? 17 inputs port function hl in high-impedance state fifo2 write hh in high-impedance state mail2 write l l x in high-impedance state none l h x active, mail1 register none
cy7c43646 cy7c43666 cy7c43686 37 table 5. fifo1 flag operation (cy standard and fwft modes) [47] number of words in fifo memory [62, 63, 64, 65] synchronized to clkb synchronized to clka cy7c43646 cy7c43666 cy7c43686 efb /orb aeb afa ffa /ira 0 0 0 l l h h 1 to x1 1 to x1 1 to x1 h l h h (x1+1) to [1024 ? (y1+1)] (x1+1) to [4096 ? (y1+1)] (x1+1) to [16384 ? (y1+1)] h h h h (1024 ? y1) to 1023 (4096 ? y1) to 4095 (16384 ? y1) to 16383 h h l h 1024 4096 16384 h h l l table 6. fifo2 flag operation (cy standard and fwft modes) [47] number of words in fifo memory [63, 64, 66, 67] synchronized to clka synchronized to clkc cy7c43646 cy7c43666 cy7c43686 efa /ora aea afc ffc /irc 0 0 0 l l h h 1 to x2 1 to x2 1 to x2 h l h h (x2+1) to [1024 ? (y2+1)] (x2+1) to [4096 ? (y2+1)] (x2+1) to [16384 ? (y2+1)] h h h h (1024 ? y2) to 1023 (4096 ? y2) to 4095 (16384 ? y2) to 16383 h h l h 1024 4096 16384 h h l l table 7. data size for word writes to fifo2 size mode [68] write no. data written to fifo2 data read from fifo2 bm size be c 9 ? 17 c 0 ? 8 a 27 ? 35 a 18 ? 26 a 9 ? 17 a 0 ? 8 hlh1ababcd 2cd h l l 1cdabcd 2ab notes: 62. x1 is the almost empty offset for fifo1 used by aeb . y1 is the almost full offset for fifo1 used by afa . both x1 and y1 are selected during a fifo1 reset or port a programming. 63. when a word loaded to an empty fifo is shifted to the output register, its previous fifo memory location is free. 64. data in the output register does not count as a ? word in fifo memory ? . since in fwft mode, the first word written to an empty fifo goes unrequested to the output register (no read operation necessary), it is not included in the fifo memory count. 65. the orb and ira functions are active during fwft mode; the efb and ffa functions are active in cy standard mode. 66. x2 is the almost empty offset for fifo2 used by aea . y2 is the almost full offset for fifo2 used by afc . both x2 and y2 are selected during a fifo2 reset or port a programming. 67. the ora and irc functions are active during fwft mode; the efa and ffc functions are active in cy standard mode. 68. be is selected at master reset. sizec must be static throughout device operation.
cy7c43646 cy7c43666 cy7c43686 38 table 8. data size for byte writes to fifo2 size mode >@ write no. data written to fifo2 data read from fifo2 bm size be c 0 ? 8 a 27 ? 35 a 18 ? 26 a 9 ? 17 a 0 ? 8 hhh1 a abcd 2b 3c 4d hhl 1 d abcd 2c 3b 4a table 9. data size for word reads from fifo1 size mode >@ data written to fifo1 read no. data read from fifo1 bm size be a 27 ? 35 a 18 ? 26 a 9 ? 17 a 0 ? 8 b 9 ? 17 b 0 ? 8 hlhabcd1ab 2cd hllabcd1cd 2ab table 10. data size for byte reads from fifo1 size mode >@ data written to fifo1 read no. data read from fifo1 bm size be a 27 ? 35 a 18 ? 26 a 9 ? 17 a 0 ? 8 b 0 ? 8 hhhabcd 1 a 2b 3c 4d hhl abcd 1 d 2c 3b 4a
cy7c43646 cy7c43666 cy7c43686 39 document #: 38-00701-c ordering information 1k x36/18x2 tri bus synchronous fifo speed (ns) ordering code package name package type operating range 7 cy7c43646-7ac a128 128-lead thin quad flat package commercial 10 cy7c43646-10ac a128 128-lead thin quad flat package commercial 15 CY7C43646-15AC a128 128-lead thin quad flat package commercial 4k x36/18x2 tri bus synchronous fifo speed (ns) ordering code package name package type operating range 7 cy7c43666-7ac a128 128-lead thin quad flat package commercial 10 cy7c43666-10ac a128 128-lead thin quad flat package commercial 15 cy7c43666-15ac a128 128-lead thin quad flat package commercial 16k x36/18x2 tri bus synchronous fifo speed (ns) ordering code package name package type operating range 7 cy7c43686-7ac a128 128-lead thin quad flat package commercial 10 cy7c43686-10ac a128 128-lead thin quad flat package commercial 15 cy7c43686-15ac a128 128-lead thin quad flat package commercial 15 cy7c43686 ? 15ai a128 128-lead thin quad flat package industrial
cy7c43646 cy7c43666 cy7c43686 ? cypress semiconductor corporation, 2000. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagram 128-lead thin plastic quad flatpack (14 x 20 x 1.4 mm) a128 51-85101-a

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